Research on multi-time scale doubly-fed wind turbine test system based on FPGA+CPU heterogeneous calculation

1 Introduction

To achievement the energy conservation and environmental protection,the replacement of traditional fossil energy by renewable energy has become an irreversible trend.According to statistics,the installed capacity of wind power has reached 148.6 GW and the installed capacity of photovoltaic has reached 77.4 GW in 2016 in China.By 2020 in China,wind power installed capacity will reach 500 GW,photovoltaic installed capacity will reach 470 GW.With the proportion of renewable energy increasing,the grid gradually presents the characteristics of a high proportion of renewable energy [1].The major equipment of power system is no longer the traditional rotating electric machine and becomes low-inertia power electronic converters of renewable energy.In this situation,the renewable energy equipment and the grid equipment presents complex interaction.

The traditional test for the renewable energy system focuses on the electrical characteristics of the devices,and it is always implemented on a dynamic physical system.The motor drive is the core of the dynamic physical system.There are two schemes to realize the motor drive:First,the motor adopts the DC motor with the closed loop governor,but the control process is complicated and the motor needs an auxiliary motor to start.In addition,there is a restriction that the rotating motor must be the same type as the tested wind turbine.

Second,the motor is driven by a full-power inverter with variable-frequency speed control system in order to simulate the characteristics of the wind turbine.In this scheme,the companion motor can utilize different types of motors.This kind of test system can also be applied to permanent magnet synchronous motor test [2].However,the wind turbines are directly connected to the distribution network,where the interaction between the wind turbines and the power grid is not considered.The grid with a high proportion of renewable energy can not ignore these interactions.Therefore,the physical system for renewable energy tests has been unable to meet the requirements of the grid with the high proportion of renewable energy [3].

The digital-analog hybrid simulation system can simulate the grids of the test system in the digital simulation system and the back-to-back converter and the wind turbine controller in the analog simulation system.The analog simulation system is connected to the digital simulation system through I/Os.The dynamic characteristics of the wind turbine are mainly determined on its back-to-back converter and controller,which remains on the analog side.Because grids are simulated in the digital system,the interaction between the wind turbine and the grid can be simulated.This kind of the simulation system not only retains the advantages of the dynamic physical system,but also simulates the interaction between the test object and the grid,which is difficult to simulate in the dynamic physical system.

RTDS and RTLAB have proposed a test system for DFIG based on the digital simulation.The RTDS wind turbine test scheme adopts the digital-analog hybrid simulation method [4].All power circuit of the test system is simulated in the digital side with a small time step of 2us.The simulation precision is high.However,the RTDS is a complete imported system from hardware to drive and software,bases on POWER PC and highperformance DSPs.Therefore,this test system has high cost and is difficult to be widely used.RTLAB wind turbine test system generally supports a digital-analog hybrid simulation system,in which the digital simulation is in a server with Intel CPUs.The simulation step size is relatively larger(20 μs), which makes it difficult to accurately simulate the dynamics of the back-to-back converter in the wind turbine [5].

A domestic company named Yuankuan Energy Science and Technology proposes a DFIG test system based on the LABVIEW platform [6].The test system uses a joint simulation system of FPGA+CPU,which can realize realtime simulation in microseconds.However,the scale of the simulation is limited in this platform.The system can only simulate no more than one wind turbine,and the grid characteristics cannot be simulated too [7].

A DFIG test system based on digital-analog hybrid simulation is studies in this paper.This system is based on the multi-time scale parallel simulation method.The multitime scale decoupling algorithm divides the whole system into two subsystems:small(fast)step system and large(slow)step system.In this method,it is avoided to simulate the whole system using a small time step.The CPU+FPGA hardware architecture is proposed to simulate DFIG test system.FPGA speed up the small time scale simulation to achieve the real-time for the proposed test system [8-9].

The research in this paper relies on the ADPSS simulation platform.The ADPSS simulation platform is Advanced Digital Power System Simulator developed by China Electric Power Research Institute.It can be applied in power grid planning,operational analysis and test.Currently,there are 70 users nationwide.It has a market share of 40 percent.

2 Principle of DFIG test system

2.1 The overall structure of DFIG system

The DFIG test mainly is used to verify the dynamic characteristics of the wind turbine under various grid faults and study the interaction between DFIGs and grids.Therefore,the simulation accuracy of the dynamic characteristics of the DFIG is a key indicator of the test capability.

The DFIG is mainly composed of the power circuit and controllers.The power circuit mainly includes transformers,generators,converters,chopper and so on.These main components have relatively accurate EMT models.However,the converters designed by different wind turbine manufacturers have a wide variety of internal logic.In addition,the controllers of the converter also has their intellectual property,whose internal logic is a “black box”.

Under such circumstances,digital simulation is applied to power circuits,and the control protection of the converter and the chopper bar are driven by the real devices.At the same time,the digital power circuit and the real devices are connected by feeble electricity signals to form a signal closed-loop system.

Fig.1 The overall structure of the DFIG system

The test scheme is shown in Fig.1.The DFIG test system includes digital models of DFIG,the physical controller and the signal connection system.

2.2 The digital simulation model of power circuit of the DFIG

The power circuit of the DFIG includes a double fed induction motor,a back-to-back converter and a Crowbar system.

(1)Induction motor model

The induction motor model uses the traditional dq0 motor model [10],wherein the formula for the stator side winding is:

Where in Ka represents the inverse transformation matrix of the stator and KA represents the inverse transformation matrix of the rotor in Parker transform,Gsabc represents the admittance matrix of the stator on the stator side,GsABC represents the admittance matrix of the rotor on the stator side.idq0equ represents the historical current source on the dq0 axis of the stator side(Direct injection into the stator side busbar).

The formula for the rotor side winding is shown as equation(2):

Where in Grabc represents the equivalent admittance matrix of the stator on the rotor side,GrABC represents the rotor equivalent equivalence admittance matrix on the rotor side.idq0equ represents the historical current source on the dq0 axis of the rotor side(Direct injection into the rotor side busbar).

The discretization of the motor rotation equation is shown as equation(3):

(2)Converter and Crowbar

The digital model of the converter is compose of freely configurable discretization switches.In order to avoid the network equation matrix changed by the switching action,the small step switches are developed by ADPSS.When being turned on,the small step switch is represented by an inductance.When being turned off,the small step switch is represented by a capacitor and resistor branch.

Fig.2 Small step switch model

In order to keep the admittance of the switch unchanged,the admittance is calculated as follows:

Another disadvantage of the small step switch is that the switching loss is too large.In order to reduce the switching loss,a switching loss compensation algorithm has been developed to reduce the switching loss [11].

A commonly-used Crowbar is as follows:

Fig.3 A typical model of Crowbar

Crowbar has a variety of typical structures [12].The Crowbar system can also perform different topologies to fit the external controller of DFIG.

3 Multi-time scale decoupling network algorithm and its application

In order to accurately respond to the trigger pulse of the controller,the DFIG converter must adopts a small time step, usually 1-2 μs.The digital simulation of the DFIG includes the motor,converter,Crowbar and filter circuits.The existing hardware is difficult to achieve real-time for the entire digital system with small time step.

A multi-time scale network technology for DFIG is proposed in this paper.The power circuit for a DFIG is divided into two parts.One is the small time scale subsystem including the converter and its nearby circuits,and the other is the large time scale subsystem including doublyfed induction motor.The small time scale subsystem uses a time step of 2 μs, the large time scale subsystem uses a time step of 50 μs.When small time scale system calculates 25 times,the large time step subsystem calculates once.The calculation effort of the digital simulation will be greatly reduced.This algorithm builds the software foundation for the real-time simulation.

3.1 Centralized component decoupling subnetwork components and error analysis

Multi-time scale network technology relies on decoupling components to get subsystem,and the decoupling components use reactance.The reactance can be equivalent to a length of transmission line.The characteristic impedance of the transmission line is Zc = L/Δt, the signal propagation time of the transmission line is Δt.

Fig.4 Transmission line based decoupling model

There is an error between the inductive component and the transmission line.The error is mainly caused by the associated capacitance of the transmission line,and the value of the associated capacitor is CTLI = Δt 2/L1.

The voltage of the interface of the inductive component vf-Exp and the voltage of the transmission line interface vf-TLI are calculated respectively as equations(5)and(6).

Since the simulation step size Δt is very small,L1CTLI =Δt2 is approximately equal to zero.It can be ignored during the derivation process.

The error can be represented as equation(8).

According to the error equation,the simulation error is related to the associated capacitance of the transmission line and the internal circuit of the model.

3.2 Parallel full implicit multi-time scale partitioning network method based on transmission line decoupling

According to the Thevenin equivalent circuit in Fig.4,the state space equation can be established as equation(9)and equation(10).

In the above formula,Xf represents the state variable in the fast subnet,represents the Thevenin equivalent voltage source of the transmission line interface in the fast subnet,represents the interface voltage,Ufint represents the injected power inside the subnet,Af,Bfint and BfT represent the parameter matrix of the fast subnet.Xs represents the state variable in the slow subnet,represents the Thevenin equivalent voltage source of the transmission line interface in the slow subnet,represents the interface voltage,Usint represents the injected power inside the subnet,As,Bsint and BsT represent the parameter matrix of the slow subnet.

Equations(9)and(10),while ignoring the mutual coupling of voltages,are still applicable to most network.

Considering the natural delay characteristics of the transmission line,the signal transfer equation of the interface is obtained as equation(11):

Discretize equations(9)and(10),and combine equation(11),we can get the system equation as shown in equation(12).

In the above formula,fs（Usint,Ufint） and ff（Usint,Ufint）represent the functions related to Usint,Ufint in the subnet.The current and future values of Usint,Ufint can be obtained directly from the expression.Xs(mk)can be calculated directly by Xf(mk-m+i-1)and Xs(mk-2m+i).Unknown variables are not coupled to each other.Therefore,the large step system and the small step system equation are decoupled,and can be independently and parallelly solved in a large step,and the simulation efficiency is greatly improved.

3.3 Multi-time scale calculation process for transmission lines

The basic flow of a multi-time scale parallel algorithm based on transmission line decoupling is shown in Fig.5.

Fig.5 Flow process of parallel multi-rate simulation algorithm

Assume that before the time mk-m,all calculation task has been completed and the synchronization is completed.

The process can be divided into two tasks in parallel(TASK1 and TASK2).

Task 1:Calculate Xs(mk)at mk time using implicit integrals according to historical values Xs(mk-m)and Xf(mk-m)at mk-m time; use interpolation method,according to Xs(mk)and Xs(mk-m),calculate the estimated value Xs(mk-m+1)… Xs(mk-1);

Task 2:Calculate Xf(mk-m+i)at mk-m+i time using implicit integrals based on historical values Xs(mk-2m+i)and Xf(mk-m+i-1),and continue make integration m steps from i =1 to i=m.

After the task is completed,we wait for information exchange and synchronization,and continue the simulation at the next moment.

Multi-time scale simulation algorithm based on transmission line decoupling is decomposed into Task 1 and Task 2 in a single large simulation step.The two tasks are executed in parallel without dependency.

In this research,task 2 will be implemented with a small time-step,which is 1-2 µs.With such small timestep,this task can not reach the real-time in CPUs and has been implemented in FPGA.Meanwhile,task 1 will be implemented with a large time-step of 50 µs.So that task 1 can reach the real time in CPU and has been implemented in CPU.The historical values will be exchanged between CPU and FPGA through a fast fiber communication in a large time-step as demonstrated before.

4 Heterogeneous computing technology based on FPGA+CPU

The calculation effort of the digital simulation has been greatly reduced,when the DFIG test system utilizes the multi-time scale algorithm.But,relying on CPUs,the small time scale is still impossible to achieve real-time.An FPGA+CPU heterogeneous computing architecture is proposed in this paper.It realizes real-time of the small time-scale utilizing the computing power of FPGAs,thus supplies real-time simulation capability for DFIG test system.

4.1 FPGA+CPU heterogeneous computing architecture

The heterogeneous computing architecture of FPGA+ CPU is based on the fiber-optic communication framework.The basic architecture is shown in the Fig.6.The simulation processor includes the CPU and FPGA simulator.The Fiber Card is responsible for the communication between the CPU and FPGA simulator.

Fig.6 FPGA+CPU heterogeneous computing architecture

The FPGA+CPU heterogeneous computing architecture includes the hardware layer,the driver layer,and the application layer.The hardware layer includes the simulation processor and the communication board.The simulation processors include CPU and FPGA.The CPU is the Intel Xeon E5 processor,and the FPGA is the Xilinx Virtex-7 690T processor.The communication board is responsible for the information exchange between the CPU and the FPGA,and converts the PCI-E signal of the CPU to the customized fiber data signal that the FPGA simulator can receive.The communication board adopts the Xilinx Kintex-7 385T customized design.The customized fiber uses the Aurora communication protocol and the communication rate reaches 2.5 Gb/s.

The driver layer is responsible for driving these hardware devices,and forming a call interface(API)that the application layer can use.The heterogeneous computing platform is based on the WR Linux 7.0 operating system,and the driver layer is based on the Intel DPDK driver framework [13].The DPDK encapsulates the data sending and receiving functions from the CPU to the Fiber Card.The Fiber Card’s IP core takes over the communication between the Fiber Card and the FPGA simulator.

The application layer includes simulation application and simulation program.The CPU runs a general electromagnetic transient simulation program,which can perform 30-50 µs electromagnetic transient network simulation(emt_cal.exe).The FPGA is loaded the small time scale electromagnetic transient simulation system,it can perform the 2 µs time step electromagnetic transient simulation network.

4.2 FPGA-based small time scale simulation system

It is a difficult point to load the small time scale electromagnetic transient simulation system on the FPGA.

FPGA is not a general-purpose processor,but a dedicated chip,and it cannot run high-level language programs.The electromagnetic transient simulation logic should be implemented on the FPGA by using hardware circuits according to the chip design method.

Fig.7 Topology of small time-step simulator

The functions of the small time scale electromagnetic transient simulation system are shown in Fig.7,which includes the core calculation module,component area,large and small time step interface module,UD calculation module and AO/DI interface.

(1)Core calculation module

The small time scale simulation system running on the FPGA is a small-scale complete electromagnetic transient simulation system,its core task is to solve a linear equation and complete it in the core calculation module.

The basic work of the core computing module is to calculate the product of matrices and vectors in real time and efficiently,which is x = GAC-1y,wherein GAC-1 is calculated by the server at the initialization stage of the simulation and written into the relevant storage unit of the FPGA.The core of this calculation is to implement matrix and vector multiplication in parallel.The system uses a multiply-accumulate structure in this paper.

The multiply-accumulate structure is a cyclic multiply accumulator structure based on the underlying basic processing unit(PE unit).It not only effectively reduces the processing delay of the core computing module,but also shows a shorter processing time and flexibility for the lowdimensional matrix.

Fig.8 Matrix multiply model

(2)Component area

The component area is the physical component description part of the simulation program,which stores the relevant variables and results of the component model in the simulation,and completes the updating of some component variables.The small time scale electromagnetic transient simulation system includes:single phase series RLC component(SLA); three phase series RLC component(LA); single phase transformer component(STB); three phase transformer component(TB); time control switch(BRK-1); thyristor(BRK-5); GTO(BRK-6); IGBT switch pair(BRK-8); single-phase controllable voltage source(CVS); single-phase controllable current source(CIS); single-phase common voltage source(SCV); single-phase common current source(SCI); three-phase common voltage source(CV); three-phase common current source(CI); distributed parameter network decoupling element(LC).

(3)Interface module

The small time scale electromagnetic transient simulation system is a network model of a part of the power system containing power electronic equipment,and adopts a small time step size due to the requirement of simulation precision.

Small step simulation and large step simulation together simulate a complete power system,and decoupling and parallel computing is implemented by specific simulation algorithms.So data exchange and precise synchronization are required between the two simulation system.The small step size simulation system obtains the required signal from the large step simulation system through the interface,and outputs the signal for the large step size simulation system.

(4)UD calculation module

UD(User Define Interface)is a user-defined model,including UD control module and UD calculation module.Since the interface model receives some control signals from the large step system,these control signals must be processed and input to the UD calculation module,so a UD control module is added as a buffer medium.The UD calculation module implements user-defined calculations.This module is independent of the network calculation module.It includes four arithmetic operations and logic operations.The calculation results are transmitted to the component area to change the response characteristics of certain components.

There are two input information channels of the UD:a channels for interactive information of the interface model; a channels for external control information.Specifically,the parameters of the UD-built model may be passed from the large step system,so the interface model should contain UD control information.In addition,the input signal(DI)of the external control system is used to control some of the switching elements.

(5)AO/DI interface

In the small time scale simulation process,the AO/DI interface can be used to form a closed loop with the external actual control device.The AO/DI interface is mainly responsible for the analog signal output and the switch signal input,and output the component state in the component area through the AO channel.The switch signal is obtained from the outside to change the component state.

The DI input interface module is mainly responsible for the input of the external actual control device switch signal.It is required that each FPGA emulation board should have 36 road DI interfaces,and all channels are transmitted to the I/O ports of the FPGA after high-speed optical isolation.

The high level of the DI signal is 5 V,and the low level is 0 V,so it needs to be converted.The signal input is optically isolated,with an isolation voltage greater than 500 V DC and an input delay of less than 10 ns.

The FPGA is required to capture the transition time of the binary signal and apply it to the time scale relative to the simulation step.The time scale accuracy should be better than 10 ns.The simulation program can improve the simulation accuracy according to the signal transition time.

(6)The communication interface of control closed loop

In the small time scale simulation process,the optical fiber communication interface can also form a closed loop with the external actual control device,and the communication method is used to exchange information.The control signal of the external control device is collected by designing an I/O board,and the external control device communicated with the small time scale simulation platform through the optical fiber interface.Similarly,the control signal outputted by the small time scale simulation platform is transmitted to the I/O board.The I/O board controls the external device through D/A conversion.

5 Case study

5.1 Test system structure of DFIG test system

The DFIG closed-loop test capability verification adopts the method proposed in this paper.The external DFIG controller adopts the DFIG controller developed based on the LABVIEW platform.

The closed-loop test platform of DFIG is based on the ADPSS.The power circuit of the closed-loop DFIG test system is shown in the Fig.9.

The FPGA part and CPU part of power circuits are decoupled through the decoupling components,which are two transmission lines,Stator transmission line and Rotor transmission line.The parameters of these transmission lines are demonstrated in Table 1.

Fig.9 The digital part structure of wind turbine system

The main parameters are shown in Table 1-3.

Table 1 Parameters of the Primary system

Variable Value Variable Value Stator side circuit resistance 3.5 e - 8 Ω Rotor side circuit resistance 3.5 e - 8 Ω Stator side circuit inductance 0.1386 mH Rotor side circuit inductance 0.0846 mH Stator side circuit capacitance 18.45 μF Rotor side circuit capacitance 30 μF Stator side circuit length 1 km Rotor side circuit length 1 km Damping resistor 1000 Ω

Table 2 Parameters of the induction machine

Variable Value Variable Value Rated Capacity 1.5 MVA Stator resistance Rs 0.00892 p.u.Rated power 1.5 MW Stator leakage reactance Xls 0.07323 p.u.Rated frequency 50 Hz D-axis excitation reactance Xmd 2.74323 p.u.Rated line voltage 0.69 kV Q-axis excitation reactance Xmq 2.74323 p.u.Stator grounding method Grounding Rotor cage resistance Rrl 0.00749 p.u.Rotor grounding method Grounding Rotor cage reactance Xlrl 0.12599 p.u.Initial state Steady state Mass block 1 Initial slip ratio 0.1395 Inertia Tj1 20 p.u.

Table 3 Back to back converter

Variable Value Variable Value Rotor side converter reactor resistance 0.0001 p.u. Grid-side converter reactor resistance 0.005 p.u.Rotor side converter reactor inductance 0.0247 p.u. Grid-side converter reactor inductance 0.1169 p.u.Rotor converter filter resistance 1000000 Ω Grid-side converter filter resistor 1000000 Ω Rotor converter filter capacitor 2.1645e-04F Grid-side converter filter capacitor 1.8314e-06F DC capacitor C1 0.235F DC capacitor C2 0.235F

5.2 Accuracy verification

In order to verify the accuracy of the proposed simulation method,the multi-time scale simulation and FPGA+CPU heterogeneous computing,two kind of simulation results are compared.First results come from the DIFG test system using all proposed methods.Second results come from the off-line simulation with a small timestep and no decoupling elements for whole DFIG test system.In order to ignore the impact of the control system,a typical control model is utilized and built at ADPSS for both kinds of the simulation.

The comparison of both simulation methods is demonstrated in Fig.10 and Fig.11.The blue line represents the simulation result of the offline simulation with only small time step.The black line represents the simulation result of the real-time simulation with the proposed method in FPGA+CPU heterogeneous computation.Isa is stator current of DFIG.Ira is the rotor current of DFIG.Vdc+ is the positive voltage of the DC sides in the back-to-back convertor.

Fig.10 presents the dynamics of the DC voltage step change,while Fig.11 presents the dynamics under a singlephase AC fault lasting 1s.Rotor current of DFIG has some phase shift for different simulation method in Fig.10.It is caused by the different steady state of controller and not impact the dynamic characteristics of DFIG.Except that,all results of both simulation methods match well,it means that the proposed simulation method can ensure the simulation accuracy and can be utilized in the DFIG test system.

It is concern that the decoupling elements and multitime scale simulation can introduce errors to the test system.However,these errors have limited impacts on the dynamics of DFIG in the steady state condition and fault condition.Meanwhile the realization of the real-time is the major contribution and benefits in this technology.In facts,the motor can also be simulated in FPGA,but it will consume lots of FPGA resources and limit the other functions in FPGA.Thus,the proposed technology is a compromise on economy and feasibility.

Fig.10 Step change of DC voltage

Fig.11 Fault Ride-through

5.3 Test results

Two tests of the DFIG test system have been carried out,which are the step-change of DC voltage under steady state and the fault ride-through under a disturbance of the singlephase earthing.The step change of DC voltage can test the control characteristics and dynamic responses under the steady state.The fault ride-through can test the dynamics and control schemes under the disturbance.

(1)Step change of DC voltage

The operation monitor board of NI controller,which is presented in Fig.9,has being monitoring the AC voltage of the DFIG,the stator active power,the stator reactive power,the stator current,the rotor active power,the rotor reactive power,the DC voltage at the Back-to-Back converter and the AC current of the grid sides at the Back-to-Back converter.

Fig.12 Operation monitor board

Fig.13 Step change of DC voltage

In Fig.13,the step change of DC voltage starts at 6.4 s.It is noted that the time in Fig.13 represents the time from the beginning of the wave recording.The DC voltage changes from 1700 V to 1400 V,which finished within 100 ms.During the step change,the AC voltages(Vgridabc),the rotor current(Ir_abc)and the stator current(Is_abc)are not disturbed and the DFIG is running on steady state.

(2)Fault Ride-through tests under the AC fault

In Fig.14,a single-phase fault happens at 9.3 s,which lasts about 1 s.During this fault,the state current at the phase with the fault increase,while the state currents at the phase without the fault decrease.After the fault clearance,the stator currents recover rapidly under the control.In addition,the fault brings the wave distortion of the rotor current,which is contributed by the distorted DC voltage.After the fault,the rotor current is controlled to the reference value rapidly.The DC voltage can not be controlled during the fault.

6 Conclusions

With more renewable energy interconnecting into the power grid,the test capability of renewable energy devices attracts a hot spot of concern.The traditional dynamic physical simulation has been difficult to adapt to the future test requirements of renewable energy due to high cost and low flexibility.The digital simulation-based DFIG test system proposed in this paper,which has high flexibility and good economy and will become the mainstream solution to enhance the renewable energy test capability.

Fig.14 Fault Ride-through

The DFIG test system proposed in this paper adopts multi-time scale sub-network simulation technology to,in which the motor is simulated with the large time scale.It avoids the small time-step simulation for whole the test system and greatly reduces the calculation efforts.

The calculation effort of the digital simulation has been greatly reduced,when the DFIG test system utilizes the multi-time scale algorithm.But,relying on CPUs,the small time scale is still impossible to achieve real-time.This paper proposes an FPGA-based EMT simulation technology and a CPU+FPGA heterogeneous simulation technology to realize the real-time simulation.The FPGA-based EMT real-time simulation includes the core computing module,component area,interface module,UD calculation module,AO/DI interface and timing control area,etc.,which can provide users with the flexibility to build the power circuit.

A LABVIEW controller is established in this paper as a test system to replace the real devices.It proves that the proposed DFIG test system can connect the external control and protection system.The dynamic characteristics of this test system are consistent with the theoretical results,which meets the dynamics test requirements of the DFIGs.Meanwhile,this scheme lays the foundation for providing more power equipment test systems for the ADPSS simulation system in the future.

Acknowledgements

This work was supported by the State Grid Science and Technology Project(Title:Technology Research On Large Scale EMT Real-time simulation customized platform,FX71-17-001).